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STK20N75F3
N-channel 75 V, 0.0065 , 20 A, PolarPAK(R) STripFETTM Power MOSFET
Features
Type STK20N75F3

VDSS 75 V
RDS(on) max < 0.0079
Ultra low top and bottom junction to case thermal resistance Extremely low on-resistance RDS(on) Very low switching gate charge Fully encapsulated die 100% matte tin finish (in compliance with the 2002/95/EC european directive) High avalanche ruggedness PolarPAK(R) is a trademark of VISHAY Figure 1.
PolarPAK(R)
Application
Switching applications
Description
This STripFETTM III Power MOSFET technology is among the latest improvements, which have been especially tailored to minimize on-state resistance providing superior switching performances.
Table 1.
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Internal schematic diagram
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Bottom View
Top View
Device summary
Marking 20753 Package PolarPAK(R) Packaging Tape and reel
Order code STK20N75F3
June 2009
Doc ID 14849 Rev 2
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www.st.com 15
Contents
STK20N75F3
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ........................... 6
3 4 5
Test circuits
.............................................. 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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STK20N75F3
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS ID (1) ID IDM (2) PTOT (1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Derating factor Value 75 20 20 12.5 80 5.2 0.0416 600 -55 to 150 Unit V V A A A W
EAS (3) Tj Tstg
Single pulse avalanche energy Operating junction temperature Storage temperature
1. When mounted on FR-4 board of 1inch2, 2 oz Cu and 10 sec 2. Pulse width limited by package 3. Starting TJ = 25 C, ID = 20 A, VDD = 50 V
Table 3.
Symbol Rthj-amb(1) Rthj-c(2) Rthj-c(3)
Thermal data
Parameter
Thermal resistance junction-amb
Thermal resistance junction-case (top drain) Thermal resistance junction-case (source)
1. When mounted on FR-4 board of 1inch2, 2 oz Cu and 10sec 2. Steady state
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3. Measured at source pin when the device is mounted on FR-4 board in steady state
Pr e
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(s)
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C
W/C mJ
Typ. 20 0.8 2.2
Max. 24 1 2.7
Unit C/W C/W C/W
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Electrical characteristics
STK20N75F3
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS= 0 VDS = Max rating, VDS = Max rating,Tc=125C VGS = 20V VDS= VGS, ID = 250 A VGS= 10 V, ID= 10 A 2 Min. 75 1 10
100
Typ.
Max.
Unit V A A nA V
0.0065 0.0079
Table 5.
Symbol Ciss Coss Crss Qg Qgs Qgd RG
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Test conditions
Gate input resistance
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Table 6.
Pr e
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(s)
so Ob VGS =10 V (see Figure 14)
VDS =25 V, f=1 MHz, VGS=0
te le
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Min. -
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Typ. 2480 446 41 40.4 11.6 9.9
s) t(
-
4
Max.
Unit pF pF pF nC nC nC
VDD= 38 V, ID = 20 A
-
f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain
-
0.85
-
Switching times
Parameter Test conditions VDD= 37.5 V, ID= 10 A, RG=4.7 , VGS= 10 V (see Figure 13) VDD=37.5 V, ID= 10 A, RG=4.7 , VGS= 10 V (see Figure 13) Min. Typ. 15.6 16.2 Max. Unit ns ns
Symbol td(on)
Turn-on delay time Rise time
-
td(off) tf
Turn-off delay time Fall time
37.8 4
-
ns ns
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STK20N75F3
Electrical characteristics
Table 7.
Symbol ISD ISDM
(1)
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on Voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 20 A, VGS=0 ISD= 20 A, di/dt = 100 A/s, VDD=60 V, Tj=150C (see Figure 18) Test conditions Min. Typ. Max. 20 80 1.2 49.7 103.6 4.2 Unit A A V ns nC A
-
VSD(2) trr Qrr IRRM
-
-
1. Pulse width limited by package 2. Pulsed: pulse duration = 300s, duty cycle 1.5%
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Electrical characteristics
STK20N75F3
2.1
Figure 2.
ID (A) 100
Electrical characteristics (curves)
Safe operating area
AM04908v1
Figure 3.
Thermal impedance
s ai are n) his DS(o t in x R ion ma y rat pe ed b O it Lim
Tj=150C Tc=25C Sinlge pulse
10
1
10ms 100ms 1s
0.1 0.01 0.1
1
10
VDS(V)
Figure 4.
ID (A) 200
Output characteristics
AM04909v1
Figure 5.
ID (A) 250 200
Transfer characteristics
VGS=10V 6V
150
100 5V 50
0 0
1
2
3
4
5
6
Figure 6.
BVDSS (norm) 1.10
Normalized BVDSS vs temperature
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1.05 1.00 0.95
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7
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150
Pr te le
2 4
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VDS=4V
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AM04910v1
8 VDS(V)
6
8
10 VGS(V)
Figure 7.
RDS(on) () 7.0 6.9 6.8 6.7 6.6 6.5 6.4 6.3 6.2 6.1 0
Static drain-source on resistance
AM04912v1
AM04911v1
0.90 -50 0 50 100 150 TJ(C)
5
10
15
20
ID(A)
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STK20N75F3 Figure 8.
VGS (V) 12 10 8 4000 6 4 2 0 0 10 20 30 40 50 Qg(nC) 3000
Electrical characteristics Capacitance variations
AM04914v1
Gate charge vs gate-source voltage Figure 9.
AM04913v1
C (pF) 7000 6000 5000
VDD=37.5V ID=20A
Ciss 2000 Crss 1000 Coss 0 0 10 20 30 40 50 60 70 VDS(V)
Figure 10. Normalized gate threshold voltage vs temperature
VGS(th) (norm) 1.2
AM04915v1
Figure 11. Normalized on resistance vs temperature
RDS(on) (norm) 2.1 1.9 ID=10A VGS=10V 1.7 1.5
1.0
0.8
0.6
0.4 -50 0 50 100
150
Figure 12. Source-drain diode forward characteristics
VSD (V)
O
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0.8 0.7 0.6 0.5 0.4 0
0.9
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TJ(C)
so Ob 1.1 0.9 0.7 0.5
1.3
te le
-50 0
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AM00895v1
50
100
150
TJ(C)
AM04917v1
TJ=-50C
TJ=25C
TJ=175C
5
10
15
20
ISD(A)
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Test circuits
STK20N75F3
3
Test circuits
Figure 14. Gate charge test circuit
VDD 12V
2200
Figure 13. Switching times test circuit for resistive load
47k 100nF
1k
RL VGS VD RG PW D.U.T.
F
3.3 F
VDD Vi=20V=VGMAX
2200 F
IG=CONST 100 2.7k 47k PW 1k D.U.T. VG
AM01468v1
Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit
A D G S B 25 D.U.T.
A FAST DIODE B
A L=100H B D G 3.3 F 1000 F
RG
S
Figure 17. Unclamped inductive waveform
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AM01469v1
3.3 F
VDD
Vi
Pw
AM01471v1
AM01470v1
Figure 18. Switching time waveform
ton tdon tr toff tdoff tf
V(BR)DSS
90%
90% 10%
0 VDD
10%
VDS 90%
VGS
AM01472v1
0
10%
AM01473v1
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STK20N75F3 Figure 19. Gate charge waveform
Test circuits
Id Vds Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
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Package mechanical data
STK20N75F3
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
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Package mechanical data
Table 8.
Ref.
PolarPAK(R) (option "L") mechanical data
mm Min. Typ. 0.80 Max. 0.85 0.05 0.48 0.41 2.19 0.89 0.23 0.20 6 5.74 5.01 4.75 0.23 0.45 0.31 0.45 4.22 1.08 1.37 0.24 4.37 1.13 0.41 0.56 0.51 0.56 0.58 0.51 2.29 1.04 0.33 0.25 6.15 5.89 5.16 4.90 0.68 0.61 2.39 1.19 0.43 0.30 6.30 6.04 5.31 5.05 0.019 0.016 0.086 0.035 0.009 0.008 0.236 0.226 0.197 0.187 0.009 0.023 0.020 0.090 0.041 0.013 0.010 0.242 0.232 0.203 0.193 Min. 0.030 inch Typ. 0.031 Max. 0.033 0.002 0.027 0.024 0.094 0.047 0.017 0.012
A A1 b1 b2 b3 b4 b5 c D D1 E E1 H1 H2 H3 H4 K1 K2 K3 K4 M1 M2
0.75
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M3 M4 P1 T1 T2 T3 T4 T5 <
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3.43 0.22 0.05 0.15 3.48 0.56 1.20 3.90
4.30
(s) ct
4.50 3.58 0.20 3.64 0.76
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4.52 1.18
so
Pr te le
0.018 0.012 0.018 0.166 0.043 0.054 0.009 0.169 0.135 0.009 0.002
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0.238 0.209 0.199 0.022 0.020 0.022 0.178 0.046
0.248
0.016
0.172 0.044
4.70 3.73
0.177 0.141
0.185 0.147
0.25 4.10 0.95
0.006 0.137 0.022 0.047 0.154
0.008 0.143 0.030
0.010 0.161 0.037
0.18 0 10
0.36 12 0
0.007 10
0.014 12
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Package mechanical data
STK20N75F3
Figure 20. PolarPAK(R) (option "L") drawings
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STK20N75F3 Figure 21. Recommended PAD layout
Package mechanical data
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Revision history
STK20N75F3
5
Revision history
Table 9.
Date 01-Jul-2008 22-Jun-2009
Document revision history
Revision 1 2 First release Document status promoted from preliminary data to datasheet. Changes
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bs O
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
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